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feat(plc): analyse graphical logic (FBD/LD) from PLCopen XML [#165] #169

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sharang merged 1 commits from feat/plc-graphical-languages into main 2026-07-16 11:43:50 +00:00
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Sharang ParnerkarandClaude Opus 4.8 aab22d6492 feat(plc): analyse graphical logic (FBD/LD) from PLCopen XML
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CODESYS control logic is frequently written in graphical languages, but the
scanner only understood Structured-Text bodies — FBD/LD/SFC were skipped, so
their comm calls, hardcoded arguments and safety writes went unseen.

Translate FBD/LD networks to synthetic ST and run them through the existing ST
parser + rules: blocks become calls (`TypeName(pin := arg, …)`), out-variables
and coils become assignments, and input pins are resolved by tracing
`connectionPointIn`/`refLocalId` back through the network (contacts AND-chain to
the power rail; nested blocks are referenced by a synthetic result so calls are
emitted exactly once). SFC step/transition graphs are skipped, but the ST/FBD/LD
bodies embedded in their actions/transitions are still translated.

Also fixes a latent doubling bug in `collect_text`: `descendants()` yields both
an element and its child text node, so every value was collected twice. Harmless
for ST (duplicate statements landed on one synthetic line and deduped) but it
corrupted graphical single-token expressions (`502` -> `502502`,
`FALSE` -> `FALSEFALSE`). Now only text nodes are gathered.

Adds an FBD demo fixture (pump_fbd.xml) + FBD/LD/regression tests.

Part of #165 (graphical languages). Native `.project`/`.projectarchive` parsing
and SFC graph semantics remain follow-ons. Tracker #167.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-16 13:36:34 +02:00