docs(plc): soft-PLC architecture + CODESYS/Yocto lifecycle diagram (#184)
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This commit was merged in pull request #184.
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@@ -11,6 +11,72 @@ the control application *and* the device it runs on.
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| A device firmware image | Firmware SBOM / CVE (opt-in) |
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| A reachable endpoint (WebVisu, OPC UA) | DAST / pentest (opt-in) |
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## Anatomy: a soft PLC is a SoC + Linux + runtime
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A CODESYS controller is **not** a monolithic appliance like a classic Siemens
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S7. It is **PC-based ("soft") control** — commodity silicon running a
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general-purpose Linux, with a **software PLC runtime** as just another process:
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| Classic PLC (e.g. Siemens S7) | Soft PLC (CODESYS-on-Yocto, OpenPLC-on-Raspbian) |
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| --- | --- |
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| Proprietary hardware + firmware | Commodity SoC (x86 / ARM) |
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| Proprietary OS | General-purpose Linux (a **Yocto** image, or Raspbian) |
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| Proprietary runtime | Software runtime (**CODESYS Control**, or OpenPLC) |
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| STEP7 / TIA project | IEC 61131-3 control app (ST / LD / FBD / SFC) |
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Because of this, the device is built along **two independent tracks**, by
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different people, on different timelines, and shipped separately. It also
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inherits the **entire Linux / IT attack surface on top of** the OT / control
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one — which is exactly why a PLC/SPS target is treated as a **composite**:
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Certifai ingests one artifact per layer and scans each with the right pipeline.
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```mermaid
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flowchart TB
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subgraph TA["Track A · Device platform — built by the hardware OEM / vendor"]
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direction LR
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A1["Yocto / OpenEmbedded<br/>BSP + RT kernel"] --> A2["Bake in the CODESYS<br/>Control for Linux runtime"] --> A3["bitbake → device image<br/>.wic / .tar + manifest"]
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end
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subgraph TB2["Track B · Control application — built by the machine builder / customer"]
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direction LR
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B1["CODESYS IDE<br/>ST / LD / FBD / SFC + WebVisu"] --> B2["Reference CODESYS +<br/>vendor libraries"] --> B3["Compile → download<br/>to device (gateway 11740)"]
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end
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A3 --> DEV(["Running soft-PLC device<br/>SoC + Linux + runtime + control app<br/>Modbus · OPC UA · EtherNet/IP · WebVisu"])
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B3 --> DEV
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subgraph CERT["What Certifai scans — one layer per artifact"]
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direction LR
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S1["Firmware layer<br/>FirmwareStatic · SBOM · CVE"]
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S2["Control-logic layer<br/>PLC SAST — ST + FBD/LD"]
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S3["Control-app SBOM<br/>libraries + runtime → CVE"]
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S4["Running layer<br/>ICS probe · DAST (WebVisu)"]
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end
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A3 -. firmware image .-> S1
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B1 -. PLCopen XML / ST via git .-> S2
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B2 -. projectarchive (zip) .-> S3
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DEV -. live URL / provisioned .-> S4
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classDef yocto fill:#fde68a,stroke:#b45309,color:#111
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classDef codesys fill:#bfdbfe,stroke:#1d4ed8,color:#111
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classDef dev fill:#e9d5ff,stroke:#7e22ce,color:#111
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classDef cert fill:#bbf7d0,stroke:#15803d,color:#111
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class A1,A2,A3 yocto
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class B1,B2,B3 codesys
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class DEV dev
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class S1,S2,S3,S4 cert
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```
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::: tip Where Yocto fits
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Yocto is **Track A** — the *build system* for the device platform. It produces
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the Linux image and bakes in the CODESYS runtime, so it is the **firmware
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layer**, entirely separate from the control application. Hand it to Certifai as
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its own **firmware image** artifact (scanned by the firmware pipeline, not the
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PLC pipeline). The device OS need not be Yocto — Raspbian/Debian/Buildroot, or
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even an RTOS / bare-metal, are all possible — but Yocto is the common,
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product-grade industrial choice.
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:::
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## Two ways to deliver the project
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You can either **upload** the project when onboarding, or point Certifai at a
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